1. Field of the Invention
The invention relates to a thermal vias-provided cavity-down IC package structure, and in particular to a super high-efficiency thermal vias-provided cavity-down IC package structure.
2. Description of the Related Art
In a module including at least one integrated circuit (IC), a large number of electrically conductive wires is required to form a complete circuit for signal and power source inputs/outputs. In the past, there were many different types of IC packages. The common packages are a planar package, a hermetic and plastic chip carrier package and a grid array package.
In conventional and widely used IC packages, a lead frame is used to electrically connect a semiconductor chip and the external leads of a package. Since ICs are becoming increasingly more precise and complicated, the number of wires required is greatly increased with the sizes of packages remaining the same or being reduced. Therefore, the conventional lead frame cannot meet practical requirements. To resolve this problem, a new type of IC package for containing a greater number of wires is urgently required to complete more complicated circuits.
Accordingly, a ball grid array (BGA) IC package used to contain a greater number of wires was introduced. In general, BGA is a square package where solder balls are used for external electrical connections instead of lead pins. The solder balls are used to electrically connect to a printed wire board, a printed circuit board or bonding pads of other ICs.
In practice, a conventional BGA substrate is a small, double-layer or multi-layer, printed circuit board. A chip is electrically connected to the BGA substrate through a plurality of wires. Moreover, electrical connections between conductive layers in the BGA substrate are completed via plated-through-holes or metal plugs.
FIG. 1 is a schematic, cross-sectional view illustrating a cavity-down BGA IC package structure which is disclosed in U.S. Pat. No. 5,357,672 issued to LSI Logic Corporation. As shown in FIG. 1, three layers of printed wire boards 100, 102 and 104 are attached to each other through prepregs 106, 108 and 110 with a cavity 111 formed therein. A chip 112 is disposed at the center of the cavity, and is surrounded by trapezoidal edges of the 3-layer printed wire board. The trapezoidal edges are designed with bonding pads 114 and 116 thereon. Bonding pads 118 surrounding the chip 112 are electrically connected to the bonding pads 114 and 116 through bonding wires 120, and then to bumps 124 through plated through hole 122 for a signal transmission with a main board (not shown). A heat sink 130 is disposed on the back of the chip 112 for heat transfer.
In this patent, the three layers of printed wire boards 100, 102 and 104 attached to each other through prepregs 106, 108 and 110 serve as a substrate, and the cavity 111 formed in the substrate is chiefly used to contain the chip 112. Therefore, the bumps 124 can be formed on the same side as the chip 112. Compared to a general BGA IC package with a chip and bumps formed on two opposite sides, two conductive layers are saved.
In a conventional cavity-down BGA, PGA (Pin Grid Array) or multi-chip module (MCM) IC package, at least two conductive layers, such as conductive layers 126 and 128 shown in FIG. 1, are formed in a multi-layer printed wire boards serving as a substrate, with a cavity formed in the multi-layer printed wire board. Since a general chip has a thickness approximately equal to or greater than that of the substrate and the chip and solder balls are located on the same side, the contact between the solder balls and a main board is hindered during bonding and molding. For this reason, in a conventional cavity-down IC package, a chip is generally ground to have a thickness ranging from 10 to 25 mil. However, wafers are easily broken during grinding, resulting in an expensive loss of material.
Furthermore, in the conventional cavity-down BGA, PGA or MCM IC package, only one planar heat sink, such as the one 130 shown in FIG. 1, is disposed on the back of a chip. However, this heat sink design cannot meet requirements for highly integrated, high-speed ICs where a great amount of heat is generated, and all devices formed in the ICs are extremely sensitive to temperature.